CMOS (Complementary Metal-Oxide Semiconductor) type logic gates are widely used for silicon integrated circuits, though DCFL (Direct Coupled Field-Effect Transistor Logic), which is much simpler in structure compared to CMOS, is widely used for compound semiconductor integrated circuits.
In compound semiconductor integrated circuits, in particular, in MMIC (Monolithic Microwave Integrated Circuit), RF (Radio Frequency) switch circuits into which logic circuits such as decoder circuits are built, have been put into practical use and DCFL circuits are also being used in these as well.
Since these MMIC circuits are utilized in portable wireless terminals such as cellular telephones, their power consumption is a factor that influences the battery life of the terminals. In order to extend the battery life and enhance the convenience of the terminal users, lower power consumption of terminals has been demanded. Consequently, lower power consumption of the above-mentioned logic circuits has become a major concern.
The basic composition of a DCFL type logic circuit used in the above-mentioned manner will be described referring to the figures. FIG. 6A is a schematic of a DCFL type inverter. FIG. 6B is a cross sectional view of the DCFL type inverter formed on a GaAs semi-insulating substrate.
In FIG. 6B, the cross section of the upper-layer wire is omitted and only lines that represent wire are shown for sake of simplicity.
As shown in FIGS. 6A and 6B, a DCFL type logic gate is comprised of two elements; a pull-down transistor 301 and a pull-up resistor 401. The pull-down transistor 301 shown in FIG. 6B is an n channel type JFET (Junction Field Effect Transistor) and has an n type channel layer 303 formed on the surface of a GaAs substrate 302. This n type channel layer 303 is, for example, a layer implanted with Si ions.
A p type gate layer 304 is formed on this n type channel layer 303. This p type gate layer 304 is, for example, a layer diffused with Zn.
In addition, an n type source contact region 305 and n type drain contact region 306, between which the p type gate layer 304 is held, are formed on the surface layer of the n type channel layer 303. Both of the n type source contact region 305 and n type drain contact region 306 are, for example, layers implanted with Si ions.
An insulating film 307 comprised of, for example, silicon nitride film, is formed on the GaAs substrate 302. Contact holes are opened in the insulating film 307 on both of the n type source contact region 305 and n type drain contact region 306 and then through these contact holes a source ohmic electrode 308 and drain ohmic electrode 309 are formed on the n type source contact region 305 and the n type drain contact region 306, respectively. The source ohmic electrode 308 and the drain ohmic electrode 309 are, for example, formed by alloying AuGe/Ni into an ohmic junction.
A gate wire 310 is formed to connect to the p type gate layer 304 and a source wire 311 is formed to connect to the source ohmic electrode 308. A drain wire 312 is also formed to connect the drain ohmic electrode 309. The gate wire 310, source wire 311 and drain wire 312 are all metallic thin film formed from, for example, three layers of Ti/Pt/Au.
In contrast, the pull-up resistor 401 has an n type conductivity layer 402 that is formed on the surface layer of the GaAs substrate 302. The n type conductivity layer 402 is, for example, a layer implanted with Si ions. N type contact regions 403 and 404 are formed on the surface layer of the n type conductivity layer 402. Both of the n type contact regions 403 and 404 are, for example, layers implanted with a high concentration of Si ions.
Contact holes are opened in the insulating film 307 on both the n type contact regions 403 and 404, and ohmic electrodes 405 and 406 are formed through these contact holes on the n type contact regions 403 and 404, respectively. These ohmic electrodes 405 and 406 are, for example, formed by alloying AuGe/Ni into an ohmic junction.
Furthermore, an interlayer insulation film 313 is formed on the insulating film 307. A metal wire 407 (the drain wire 312) and a metal wire 408 are formed on this interlayer insulation film 313. The metal wires 407 and 408 are respectively connected to the ohmic electrodes 405 and 406, through the contact holes formed on the interlayer insulation film 313. These metal wires 407 and 408 are, for example, a metallic thin film formed from three layers of Ti/Pt/Au.
The manufacturing procedure of the logic gate shown in FIG. 6 will be described referring to FIGS. 7 and 8.
At first, as shown in FIG. 7A, the n type conductivity layer 402 implanted with n type impurity ions through a predetermined ion implantation mask is formed on a formation region 401A of the pull-up resistor 401 of the GaAs substrate 302 after forming, for example, a silicon nitride film or silicon oxide film on the GaAs substrate 302 as a through film 314 for ion implantation.
Next, as shown in FIG. 7B, the n type channel layer 303 implanted with n type impurity ions through a predetermined ion implantation mask is formed on a formation region 301A of the pull-down transistor 301 of the GaAs substrate 302. Ion implantation that forms the n type conductivity layer 402 may also be performed after performing ion implantation that forms the n type channel layer 303.
As shown in FIG. 7C, n type impurities ions are implanted onto the n type channel layer 303 and the n type conductivity layer 402 of the GaAs substrate 302 through a predetermined ion implantation mask to respectively form the n type source contact region 305 and the n type drain contact region 306 as well as the n type contact regions 403 and 404.
As shown in FIG. 7D, the through film 314 is removed and the implanted impurity ions activated by annealing.
As shown in FIG. 8E, the insulating film 307 of, for example, a silicon nitride film is formed on the GaAs substrate 302.
As shown in FIG. 8F, contact holes are opened in the insulating film 307 and then p type impurities are diffused through these contact holes to form the p type gate layer 304.
As shown in FIG. 8G, the gate wire 310 is formed on the p type gate layer 304.
As shown in FIG. 8H, contact holes are opened in the insulating film 307 on the n type source contact region 305, the n type drain contact region 306 and the n type contact regions 403 and 404. The source ohmic electrode 308, the drain ohmic electrode 309 and the ohmic electrodes 405 and 406 are formed through these contact holes.
Thereafter, as shown in FIG. 6b, the interlayer insulation film 313 is formed. Contact holes are opened in the interlayer insulation film 313 and the source wire 311, drain wire 312 and the metal wires 407 and 408 are formed.
The above-mentioned DCFL type logic gate uses a small number of gates when compared to the composition of other gates such as SCFL (Source Coupled FET Logic). Consequently, the surface area of the substrate occupied by the gates is small, which is favorable for the high integration of an integrated circuit. Further, when the pull-down transistor 301 is off, the static current consumption is held low. Because of this, there is the advantage of low power consumption.
Compared to CMOS however, the power consumption is high. This is due to the fact that when the pull-down transistor 301 is on, static current is consumed through the pull-up resistor 401 in the logic gate shown in FIG. 6.
In contrast to this, when the pull-up resistor 401 is replaced with a p channel type FET 501 as shown in FIGS. 9A and B, the static current consumption when the pull-down transistor 301 is on can be reduced. Consequently, according to the composition shown in FIGS. 9A and B, although the power consumption is still high compared to CMOS, it can be brought close to the power consumption of CMOS.
FIG. 9A is a schematic of a complementary logic gate that has a p channel type transistor as the pull-up transistor 501. FIG. 9B is a cross section thereof. As shown in FIG. 9B, the composition of the pull-down transistor 301 is the same as that in FIG. 6B so a description is omitted.
The pull-up transistor 501 has an n type well region 502 formed by ion implanting, for example, Si onto the surface layer of the GaAs substrate 302. In addition, a p type channel layer 503 is formed by diffusing, for example, Zn onto the surface layer of the n type well region 502. Even further, an n type gate layer 504 is formed by ion implanting, for example, Si onto the surface layer of the p type channel layer 503.
A p type source contact region 505 and p type drain contact region 506, between which the n type gate layer 504 is held, are formed on the surface layer of the p type channel layer 503. Both the p type source contact region 505 and the p type drain contact region 506 are layers formed by diffusing, for example, Zn.
Contact holes are opened in the insulating film 307 on both of the p type source contact region 505 and the p type drain contact region 506 and then through these contact holes a source ohmic electrode 507 and drain ohmic electrode 508 are formed. Both the source ohmic electrode 507 and drain ohmic electrode 508 are, for example, formed by alloying AuGe/Ni into an ohmic junction.
Further, a gate wire 509 is formed to connect to the n type gate layer 504, a source wire 510 is formed to connect to the source ohmic electrode 507 and a drain wire 511 is formed to connect to the drain ohmic electrode 508. The gate wire 509, the source wire 510, and the drain wire 511 are all comprised of metallic thin film formed from, for example, three layers of Ti/Pt/Au.
An n type well contact region 512, that contains a high concentration of n type impurities, is formed on the portion of the surface layer of the n type well region 502 other than the p type channel layer 503. An ohmic electrode 513 is formed on the n type well contact region 512. When a silicon substrate is used in place of the GaAs substrate 302 however, an ohmic junction is formed by metal wire on the silicon substrate. Because of this, including a high concentration of n type impurities in the n type well contact region is normally not required.
The procedure to manufacture the logic gate shown in FIG. 9 will be described referring to FIGS. 10 and 11.
In this case, to start, the through film 314 for ion implantation is formed using, for example, a silicon nitride film or silicon oxide film, on the GaAs substrate 302, as shown in FIG. 10A
Then, the n type well region 502 is formed on a formation region 501A of the GaAs substrate 302 of this pull-up transistor 501 by ion implanting n type impurities through a predetermined ion implantation mask.
Next, as shown in FIG. 10B, the n type channel layer 303 is formed on the formation region 301A of the pull-down transistor 301 of the GaAs substrate 302 by ion implanting n type impurities through a predetermined ion implantation mask.
It is possible to form the above-mentioned n type well region 502 after forming the n type channel layer 303.
Next, as shown in FIG. 10C, the p type channel layer 503 forms on the n type well region 502 by ion implanting p type impurities through a predetermined ion implantation mask.
It is possible to form the above-mentioned n type channel layer 303 after forming the p type channel layer 503.
Next, as shown in FIG. 10D, the n type source contact region 305 and the n type drain contact region 306 are formed on the n type channel layer 303 by ion implanting n type impurities through a predetermined ion implantation mask and the n type well contact region 512 is formed on the n type well region 502 by ion implanting n type impurities through a predetermined ion implantation mask.
As shown in FIG. 10E, the through film 314 is removed and the implanted impurity ions are activated by annealing.
As shown in FIG. 11F, the insulating film 307 of, for example, a silicon nitride film is formed on the GaAs substrate 302.
As shown in FIG. 11G, openings are respectively formed on the n type channel layer 303 between the n type source contact region 305 and the n type drain contact region 306 as well as on the insulating film 307 of the p type channel layer 503. Through these openings p type impurities are diffused to form the p type gate layer 304, the p type source contact region 505 and the p type drain contact region 506.
As shown in FIG. 11H, the gate wire 310 is formed on the p type gate layer 304. Further, the source ohmic electrode 507 and the drain ohmic electrode 508 are formed on the p type source contact region 505 and the p type drain contact region 506, respectively.
As shown in FIG. 11I, an opening is formed on the insulating film 307 between the p type source contact region 505 and the p type drain contact region 506 of the formation region 501A of the p type channel layer 503 of the pull-up transistor 501 and then n type impurities are diffused through this opening to form the n type gate layer 504.
As shown in FIG. 11J, the gate wire 509 is formed on the n type gate layer 504 and the ohmic electrode 513 is formed on the n type well contact region 512. Further, the source ohmic electrode 308 is formed on the n type source contact region 305 and the drain ohmic electrode 309 is formed on the n type drain contact region 306.
Thereafter, as shown in FIG. 9B, the interlayer insulation film 313 is formed. Contact holes are formed on the interlayer insulation film 313 to form the source wires 311, 510 and the drain wires 312, 511, and so on.
According to the composition that has a pull-up transistor as described above, the power consumption can be reduced compared to the composition that has the pull-up resistor shown in FIG. 6 although the process to form a well and a gate layer must be added to the manufacturing process. Therefore, the manufacturing cost of the semiconductor devices increases.
In the composition shown in FIG. 9, the p type channel layer 503 is formed by ion implantation of impurities into the n type well region 502 formed by ion implantation of impurities, and the n type gate layer 504 is also formed by ion implantation of impurities into the p type channel layer 503. Consequently, the impurity concentration of the n type gate layer 504 fluctuates due to the influence resulted from the condition of the plurality of ion implantation processes. Because of this, control of the threshold voltage value of the pull-up transistor 501 becomes comparatively difficult, which is a factor in reductions to the yield. Increase in the manufacturing cost due to this type of yield reduction is also a problem.